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ASIC & FPGA Design Engineer

Butler America • Grand Prairie, TX • 3h ago

Location: Grand Prairie, TX

Job ID: #72890

Pay Range: $75-88

Job Description:

You will be the Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team. Our team creates, proto@types, and fields precision engagement aerospace and defense systems for the U.S. and allied militaries, delivering cutting edge digital solutions that protect the warfighter.

What You Will Be Doing

As the Senior ASIC & FPGA Design Engineer you will act as a technical leader on one or more defense programs, shaping the architecture, verification and integration of advanced FPGA based hardware.

You will translate system level performance, safety and reliability requirements into robust programmable logic designs, while collaborating with cross functional engineers to keep the program on schedule and on budget. Your responsibilities will include:

Define architecture and design specifications for ASIC/FPGA components; write clean, maintainable RTL (VHDL, Verilog, SystemVerilog) that meets performance, power and reliability goals.

Develop synthesis, place and route and timing closure strategies to guarantee deterministic operation on target devices.

Create comprehensive test plans, simulation models and verification environments (UVM, SystemC, Python based testbenches) to validate functional correctness and timing margins.

Lead hardware in the loop (HIL) testing, board level debugging and integration with subsystem hardware.

Conduct timing analysis, power budgeting and resource utilization studies to optimize device selection and FPGA utilization.

Manage configuration control using GitLab (or equivalent), maintain version controlled repositories and ensure full traceability of all artifacts.

Produce complete design documentation-specifications, test plans, verification reports and release packages-that complies with aerospace standards.

Collaborate with systems, software, hardware, mechanical, test, manufacturing and quality teams to guarantee seamless integration and milestone compliance.

Mentor junior engineers, championing best practices in FPGA development, verification and configuration management.

Basic Qualifications :

Bachelor of Science degree in Electrical Engineering or a closely related STEM field from an accredited university; Master's degree preferred

Minimum 3 years of professional experience with FPGA design and simulation verification or a related discipline

Proficiency in HDL programming with VHDL, Verilog, and/or SystemVerilog

Experience with Xilinx/AMD toolsets (Vivado, Vitis, Vitis HLS) and UltraScale design methodology

Experience with FPGA simulation tools such as Synopsys VCS

Strong understanding of digital design principles, including timing analysis, clock domain crossing, and signal integrity

Experience with high-speed interfaces such as AXI, Ethernet, TCP/IP, PCIe, and serial protocols

Practical laboratory debug experience with high-speed oscilloscopes, spectrum analyzers, and signal generators

Familiarity with Synopsys EDA tools

Must be a US Citizen; must possess or be able to obtain a DoD Secret clearance

Desired skills :

LM/MFC design experience and missile program experience

Experience with SystemVerilog, Verilog, C/C++, MATLAB/Simulink; Synopsys Synplify, Synopsys VCS, NCSim, ChipScope tool sets

Experience with Xilinx/AMD and MicroSemi/Microchip part families, internal FPGA fabric and IP

Experience implementing NSA algorithms (e.g., AES, counter mode)

Experience managing configuration control (GitLab preferred)

Experience with Vivado and Vitis FPGA toolsets

Experience with UVM and Simulink/HDL Coder integration

Comfortable using digital oscilloscopes, spectrum analyzers, power meters, signal generators, and other test equipment

Experience with troubleshooting and debugging at board level, including FPGA validation

Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)

Strong communication, collaboration, and presentation abilities

Controls and digital loop-closure application knowledge

Networking proficiency with Ethernet switches, routers, firewalls, and debugging tools (tcpdump, Wireshark)

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