Job Details:
Job Description:
Lead DTCO initiatives for general-purpose logic semiconductor technologies in large volume manufacturing, focusing on design-process co-optimization to maximize performance, power, and area (PPA) benefits across diverse foundry customer applications
Drive Design for Manufacturability (DFM) strategies across CMOS technology platforms supporting high performance compute, mobile, mixed signal, memory controllers, and other broad market applications
Develop and implement advanced DTCO methodologies including design rule optimization, process-aware design guidelines, and manufacturing-friendly design practices for versatile logic technologies
Collaborate with design teams, process engineers, and foundry customers across multiple market segments to establish optimal design-technology interfaces and co-optimization strategies
Lead cross-functional DTCO teams to translate diverse customer requirements into manufacturable solutions while optimizing yield, performance, and cost across various application domains
Drive the development of next-generation DFM tools and methodologies ensuring compatibility with Intel's existing manufacturing processes and advanced node platforms for general-purpose logic applications
Establish and maintain DTCO design rules and guidelines for complex technology nodes serving multiple markets, including advanced patterning, device optimization, and interconnect strategies
Provide senior technical leadership and mentorship to engineers and researchers in DTCO best practices, fostering innovation in design-manufacturing co-optimization for broad-spectrum applications
Stay at the forefront of industry DTCO trends, emerging design-technology interfaces, and advanced manufacturing techniques to inform optimization strategies across diverse market segments
Responsibilities
Creates next generation device and interconnect technology by ensuring the process device performance for developing processes is world class, using deep understanding of device physics.
Evaluates device performance data, using statistics, data mining, and other data analysis techniques to collect, explore and extract insights from electrical test and process yield data.
Develops scripts, algorithms and applications to translate experimental data into intelligence in order to define future development direction.
Defines robust test structures and test programs to validate advanced design rules and reliably extract key device and interconnect parameters. Sets device and interconnect performance targets for process design kit releases and interface with design and foundry partners to address circuit level issues. Assesses silicon to simulation health and readiness for high volume manufacturing. As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry.
Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values. Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market.
Qualifications:
Required Qualifications:
7+ years of experience in DTCO and/or DFM within semiconductor foundry or advanced technology development environment with an overall minimum of 15 years of experience in the semiconductor foundry industry
Deep expertise in general-purpose logic CMOS technology DTCO, with experience supporting diverse applications including high performance compute, mobile, mixed signal, and memory controller technologies
Proven track record in foundry environment developing and implementing DTCO solutions for varied customer requirements across multiple market segments
Strong background in design-process co-optimization including experience with advanced node challenges (7nm and below preferred) for general-purpose logic applications
Extensive knowledge of manufacturing processes and DFM principles with hands-on experience in large volume manufacturing optimization for diverse product portfolios
Required exposure to foundry ecosystem with understanding of customer design flows and manufacturing constraints across various application domains
Demonstrated leadership experience in driving cross-functional DTCO teams and complex technology development programs serving multiple markets
Excellent communication and collaboration skills with ability to interface effectively with design teams, process engineers, and external customers from diverse industry segments
Advanced degree (MS/PhD) in Electrical Engineering, Materials Science, or related field with focus on semiconductor technology
Preferred Qualifications:
Experience with EDA tools for DTCO analysis and optimization across multiple application domains
Knowledge of advanced patterning techniques (EUV, multi-patterning) and their design implications for general-purpose logic
Background in yield optimization and statistical process control for diverse product mix
Experience with machine learning applications in DTCO and DFM
Understanding of various design methodologies for high performance compute, mobile, and mixed signal applications
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
US, Arizona, Phoenix, US, Oregon, Hillsboro
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US:
$262,070.00-369,980.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time @type) are subject to change.
