CMOS Device and PPA Engineer, Silicon

Google • San Diego, CA • 1d ago

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience

10 years of experience in standard cell or block-level characterization and Power, Performance, and Area (PPA) evaluation.

Experience in CMOS technology, device characterization, process integration, SPICE simulation, and physical design flows (e.g., Cadence or Synopsys).

Experience with data analysis tools (e.g., JMP, or other spreadsheet software).

Preferred qualifications:

PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.

10 years of industry experience in both Foundry and Fabless environments.

Experience in product-level testing, including yield and parametric evaluation.

Experience configuring physical design CAD flows specifically for early technology evaluation and pathfinding.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) .

Responsibilities:

Conduct in-depth Power, Performance, and Area (PPA) evaluations at the standard cell and block levels to guide technology and design decisions.

Drive Design Technology Co-Optimization (DTCO) at the standard cell and block level to achieve optimal PPA characteristics.

Leverage physical design flows and CAD tools to perform detailed analysis, identify PPA trade-offs, and propose solutions.

Develop and maintain benchmarking infrastructure and methodologies for PPA evaluation of IP and memory blocks.

Collaborate with process, circuit, and physical design teams to co-optimize technology and design for PPA.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.

Google

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