Job Details:
Job Description:
About the Role and Team
The AI Silicon Architecture and Performance Engineering team is responsible for developing and maintaining performance models that enable architecture exploration, design evaluation, scalability analysis, and performance projection for next-generation AI silicon products. These models are a critical component of the product development process, providing early visibility into architectural tradeoffs, bottlenecks, and optimization opportunities long before silicon availability.
We are seeking a highly experienced and motivated engineer to drive AI silicon performance modeling, validation, architectural analysis, and stakeholder engagement activities. The candidate will work closely with architects, performance stimulus generation teams, silicon design teams, and product stakeholders to evaluate and optimize key AI silicon subsystems that determine overall platform scalability and performance.
The role focuses on performance modeling and analysis of AI SoC communication fabrics, memory subsystems, scale-up and scale-out interconnects, host-device memory paths, and end-to-end data movement infrastructure. The successful candidate will leverage SystemC/TLM-based modeling methodologies to generate actionable insights that directly influence architecture and product decisions.
This position requires a unique combination of software development expertise, architecture understanding, analytical problem solving, and cross-functional technical leadership. The engineer will be expected to independently drive complex technical initiatives while serving as a trusted performance expert across multiple organizations.
Key Responsibilities:
AI Silicon Performance Model Development
Implement new architectural features and capabilities based on evolving product requirements.
Improve model fidelity, scalability, maintainability, and simulation performance.
Perform detailed debugging and root-cause analysis of model issues and performance anomalies.
Contribute to the evolution of modeling infrastructure, methodologies, and best practices.
Develop, maintain, and enhance SystemC/TLM-based performance models representing critical AI silicon subsystems.
Drive modeling of key architectural components including:
SoC fabrics and on-chip communication networks
Memory controllers and memory subsystem behavior
Scale-up controllers and fabrics enabling accelerator-to-accelerator communication within a node, tray, or pod
Scale-out controllers and fabrics enabling communication across nodes, racks, and larger AI clusters
Host CPU to accelerator memory paths
Local, host, and remote memory access paths
End-to-end data movement architectures
Functional Validation and Model Correlation:
Define and execute comprehensive validation strategies to ensure correctness and architectural accuracy of performance models.
Develop validation plans, regression suites, coverage methodologies, and quality metrics.
Correlate modeled behavior against architectural expectations, reference simulations, performance projections, and available hardware measurements.
Investigate and resolve discrepancies between expected and observed behavior.
Establish robust validation frameworks that improve stakeholder confidence in model-generated performance projections.
Continuously improve validation methodologies and model quality.
AI Silicon Performance Characterization and Architectural Analysis:
Design and execute performance studies covering a wide range of workloads, traffic patterns, and system configurations.
Analyze performance of communication fabrics, memory systems, and data movement paths under representative AI workloads.
Evaluate bandwidth utilization, latency characteristics, congestion behavior, traffic distribution, buffering efficiency, and resource utilization.
Characterize interactions across local memory, host memory, and remote memory domains.
Assess scalability of scale-up and scale-out architectures across increasingly larger deployment footprints.
Identify performance bottlenecks and quantify their impact on overall system throughput and efficiency.
Conduct architectural tradeoff studies to evaluate alternative design approaches.
Provide performance-driven recommendations that influence architecture and product decisions.
Performance Data Generation, Analytics and Visualization:
Develop frameworks and methodologies for large-scale performance data generation and analysis.
Create automated workflows for data collection, processing, correlation, and reporting.
Develop performance dashboards and visualization tools that simplify interpretation of complex performance data.
Define and track meaningful performance KPIs and architectural metrics.
Utilize Python-based analysis frameworks to process large datasets and generate actionable insights.
Enable efficient consumption of performance information by architects, designers, and engineering leadership.
Cross-Functional Technical Leadership and Stakeholder Engagement:
Partner closely with architecture teams, performance stimulus generation teams, silicon design teams, and product stakeholders.
Drive technical discussions related to performance methodology, architectural assumptions, workload behavior, scalability analysis, and bottleneck identification.
Review architectural proposals and provide performance-driven feedback.
Present performance studies, technical findings, and architectural recommendations to engineering leadership.
Influence product and architecture decisions through data-backed analysis and sound engineering judgment.
Act as a key technical bridge between architecture, modeling, and performance analysis organizations.
Methodology Development and Team Growth:
Drive improvements in modeling methodologies, simulation efficiency, and analysis workflows.
Identify opportunities for automation across modeling, validation, performance analysis, and reporting activities.
Establish best practices for model quality, performance characterization, and architectural analysis.
Contribute to technical mentoring and knowledge sharing across the team.
Support the development of junior engineers and future team growth initiatives.
Help cultivate a culture of technical excellence and continuous improvement.
The ideal candidate should show the following behavioral traits:
Strong quantitative reasoning and data-driven decision-making skills.Analytical and Problem-Solving Skills
Strong communication and collaboration skills.
Presentation (technical) and stakeholder management skills.
Influence engineering decisions through rigorous analysis and technical credibility.
Operate independently and deliver results in ambiguous problem spaces.
Independently solve complex technical problems.
Qualifications:
Minimum qualifications, you must possess the below minimum qualifications to be initially considered for this position.
Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, Electronics Engineering.
6+ years of industry experience in:
Performance modeling, AI silicon architecture, SoC architecture, computer architecture, performance engineering, or related domains.
SoC architecture, including on-chip communication fabrics, NoC concepts, high-speed interconnects, and scale-up/scale-out communication architectures.
Memory subsystem architecture, including memory controllers, cache hierarchies, data movement, and latency/bandwidth characterization and performance bottleneck analysis.
Software development experience in C++.
Working proficiency in Python for automation, performance analysis, data processing, and visualization.
Hands-on experience with SystemC and Transaction-Level Modeling (TLM) methodologies.
Experience developing or validating performance models for AI accelerators, SoCs, CPUs, GPUs, networking products, or complex hardware systems.
Performing architectural tradeoff analysis and performance debug and characterization studies.
This position is not eligible for Intel immigration sponsorship.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Deep understanding of AI accelerator architectures and modern AI infrastructure.
Experience modeling memory, communication, interconnect, or scalability-related subsystems.
Experience with Network-on-Chip (NoC) architecture and interconnect performance analysis.
Understanding of scale-up and scale-out architectures used in modern AI computing platforms.
Familiarity with AI/ML workloads, large language models, distributed training, and inference environments.
Experience with performance stimulus generation methodologies and workload characterization.
Experience building automated dashboards and reporting solutions using Power BI, Tableau, Grafana, Plotly, or similar technologies.
Experience evaluating large-scale distributed AI systems and accelerator clusters.
Experience mentoring engineers and providing technical leadership in cross-functional environments.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Santa Clara
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003) .
Annual Salary Range for jobs which could be performed in the US: $141,910.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time @type) are subject to change.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
